1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to the forming of a structure of contact with a deep-doped region in a silicon substrate.
2. Description of the Related Art
Certain electronic components forming integrated circuits are formed vertically. Such is the case, for example, for vertical bipolar transistors. The emitter and the base of the vertical bipolar transistor are located at the surface of the silicon wafer. The collector of the bipolar transistor is located in the substrate depth. The connection between the deep collector and the surface interconnections of the integrated circuit must then be performed.
An exemplary implementation of a conventional NPN bipolar transistor of an integrated circuit is given in FIG. 1A.
In a silicon substrate 1 of conductivity type P, ions are locally implanted to create regions 2 of conductivity type N. An epitaxial layer 3 of conductivity type N is then grown above the entire silicon surface. Silicon region 2 then becomes a buried region. As an example, the ions doping substrate 1 are boron ions with a concentration of 1×1015 at./cm3. The ions doping region 2 are arsenic ions with a concentration of 5×1019 at./cm3. The ions doping epitaxial layer 3 are phosphorus ions with a concentration of 5×1015 at./cm3.
Above buried region 2, and inside of layer 3, a bipolar transistor is formed. The bipolar transistor includes a silicon well 5, an intrinsic collector 6, a base 8, and an emitter 9.
Silicon well 5 is a silicon region, of same conductivity type N as region 2, which connects buried region 2 to the wafer surface. Intrinsic collector 6 is a silicon region of the same conductivity type as buried region 2 and is in electric contact therewith due to implanted transition region 7 of the same conductivity type as regions 6 and 2. Base 8 of the bipolar transistor is a silicon region of conductivity type P located at the substrate surface. Base 8 is formed inside of epitaxial layer 3 and is located above intrinsic collector 6. Emitter 9 is a region of conductivity type N, heavily-doped and strictly included in base 8. To laterally insulate the various elements constitutive of the bipolar transistor, trenches 4 filled with oxide are used. Base 8 is thus completely surrounded with trench 4 to be laterally isolated from silicon well 5.
FIG. 1B, which is a top view of FIG. 1A, shows trench 4 completely surrounding base 8 and collector well 5. The other regions of FIG. 1A are not shown, for clarity, on FIG. 1B. The contacting areas on the emitter, the base, and the collector, are not shown in FIG. 1B. Similarly; a possible P well surrounding the bipolar transistor to isolate it from the other integrated circuit elements has not been shown.
The operation of such a transistor is conventional. As long as the voltage between the base 8 and the emitter 9 is not positive, the electrons located in emitter 9 cannot cross the potential barrier generated by the base-emitter junction. As soon as this potential barrier lowers, an electron flow runs from the emitter 9 to the intrinsic collector 6. The electric current thus generated is directed towards the integrated circuit surface to be processed by the other elements of this circuit. The collector current successively runs through transition region 7, buried layer 2, and collector well 5.
It is desired to optimize the bipolar transistor to obtain the highest possible performance. For this purpose, those skilled in the art attempt to decrease the thickness of base 8 and to reduce all internal capacitances and resistances of the device. Constraints due to the technological process limit the reduction of the base thickness. Such is the case, in particular, when the dopants of transition region 7 or of buried region 2 diffuse towards the surface in base 8. The doping level of this base is then uncontrollable. To avoid this phenomenon, the dopant concentrations must be decreased in transition region 7 and in buried layer 2. The distance from these dopant sources to base 8 must also be increased. The internal resistances of the device then strongly increase since the doping levels decrease and the distances to be covered by the current increase. The capacitance between the collector and the substrate of the bipolar transistor must also be optimized to improve the bipolar transistor performances. This capacitance is proportional to the surface of the junction between regions 2 and substrate 1. To improve the performance of the bipolar transistor, the size of region 2 must be reduced without increasing any internal resistance of the device.
The different doping levels and the internal dimensions of the device are more and more difficult to optimize as the design rules determining the minimum dimensions usable for the device decrease.